Technical Lead Design Verification Engineer
Skills
- Proficiency in System Verilog/UVM, C, C++
- Experience with verification methodologies including directed and constrained random techniques
- Knowledge of industry-standard simulators, revision control and regression systems
- Debugging and coverage analysis skills
- Familiarity with scripting languages such as Python or Perl
Responsibilities
- Lead full verification lifecycle including planning, test writing, debugging and coverage closure
- Develop hybrid verification mechanisms combining directed and constrained random testing
- Collaborate with RTL designers to debug failures and develop test plans
- Work with software and system validation teams to execute test plans on emulation platforms
- Identify and write coverage for stimulus and corner cases to ensure high quality tape-out
Education
- Bachelor's degree in Electrical Engineering required
- Master's degree in Electrical Engineering preferred
Benefits
- Competitive base salary range $147K - $195K
- Inclusive workplace supporting diversity including veterans, LGBTQ+ and individuals with disabilities
Average salary estimate
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Our Values: Our team values are integral to who we are and how we operate as a company. Customer Focus: We are intensely focused on customers' needs. Deliver Results: We execute in order to consistently prove our promise; on time, according to s...
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